1. Field of the Invention
The present invention relates to a semiconductor memory device having memory cell transistors perpendicularly stacked on a substrate, and a manufacturing method thereof.
2. Description of the Related Art
In connection with NAND-type flash memories, there has been developed, for example, a three-dimensional stack memory wherein memory cells and select transistors constituting a memory string (NAND string) are stacked. There has also been developed a technique for collectively forming the memory cells and select transistors (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2007-266143). According to this technique, element isolation dielectric films and electrode films are alternately stacked on a semiconductor substrate, and then a memory hole is formed in the stacked films to provide a MONOS film and a control gate. However, it is difficult to form a perfectly perpendicular memory hole in this memory hole formation process. Therefore, the memory hole is tapered so that its diameter is smaller on a substrate interface side (lower side) and greater on an opposite bit line side (upper side). The difference in memory hole diameter between the substrate side and the bit line side is greater when the number of stacked layers is greater and the aspect ratio of the memory hole is higher. The variation of the hole diameter leads to a difference in electric field of the memory cells and to a variation in the thickness of the MONOS films of the memory cells. As a result, the write and erase characteristics of the memory cells are varied.